CDMA communications perform multiple access propagation by spreading information into wideband signals using spreading codes with rates higher than the rate of the information, and are roughly divided into direct sequence (DS) systems that spread modulated signals by high rate spreading codes, and frequency hopping (FH) systems. The FH system resolves each symbol into smaller elements called chips, and translates the chips into signals with different center frequency at a high speed. Since the implementation of the FH system is difficult, the DS system is generally used. The DS system recovers the original narrowband signal by despreading the wideband received input signal at a receiving end, followed by demodulation. In the despreading process, correlation detection is performed between the spreading code included in the received signal and a spreading code generated at the receiving end.
Thus, the receiver for receiving the spread signal in the DS system is usually provided with a replica (reference PN sequence) of the PN sequence (received PN sequence) in the received signal, and establishes synchronization between the reference PN sequence and the received PN sequence. FIG. 1 shows a conventional synchronization circuit using a matched filter. The received signal applied to an input terminal 10 is supplied to a memory circuit 11 with taps. The number of taps of the tapped memory circuit 11 is the same as the number of chips in a spreading code interval (that is, a processing gain PG). The outputs of the taps of the memory circuit 11 are multiplied by the reference spreading code stored in a tap coefficient circuit 13 by multipliers 12. The resultant products are summed by an integrator 14, which outputs the sum from its output terminal 16 as a correlation value 15.
Using the matched filter makes it possible to quickly establish the synchronization because the peaks of the correlation value appear at the same interval as that of the spreading code. However, since the capacity of the tapped memory circuit 11 and the number of the multipliers 12 increase in proportion to the processing gain, the power consumption of the receiver will increase with the interval of the spreading code. Therefore, the conventional synchronizing circuit is not appropriate for portable devices or mobile devices.
Using a sliding correlation detector as shown in FIG. 2 makes possible power saving and downsizing of the circuit. In FIG. 2, a received signal 21 inputted to the input terminal 10 is multiplied by a spreading code, which is generated by a spreading code replica generator 30, by a multiplier 22 to obtain the correlation between the two. The resultant product is passed through a bandpass filter (BPF) 23, followed by peak power detection by a square-law detector 24. The detected power is integrated over a fixed time (normally, .+-. one chip interval) by an integral-dump circuit 25. The integrated result is compared with a threshold value by a threshold value decision circuit 26 which decides that initial acquisition has been completed if the integrated result exceeds the threshold value, and proceeds to the next step (tracking mode). If the integrated result is less than the threshold value, the decision circuit 26 supplies a control voltage 28 to a voltage controlled clock generator (VCCG) 29 which slides the phase of the replica so that the phase of the spreading code generated by the spreading code replica generator 30 is shifted by 1/N chip interval (N is a natural number equal to or greater than one). The initial acquisition has been completed by repeating the processing until the synchronized point is found.
According to this method, it is necessary to integrate the spreading replica over the fixed time every time the replica is shifted by 1/N chip interval, and to detect the synchronized point in the interval of the spreading code by comparing the integrated result. This will lengthen the acquisition time, and hence, it is not appropriate for a system which requires a quick acquisition.
In addition, the conventional correlation detector presents another problem in that it provides a rather large error in maintaining (tracking) the synchronization.
FIG. 3 is a block diagram showing a conventional DLL (Delay Locked Loop) correlation detector 44. In FIG. 3, the same functional blocks are designated by the same numerals as in FIG. 2. The reference numeral 10 designates a spreaded signal input terminal, 102 designates a decided data output terminal, 111 denotes a multiplier, and 510 designates a delay circuit. The correlation detector 44 calculates correlations between the input modulated signal and code sequences formed by advancing and retarding the chip phase of the replica by 1/N, respectively. The correlated signals are passed through bandpass filters (BPFs) 53 and 54 which eliminate unnecessary high frequency components, and are detected by square-law detectors 55 and 56. The squared amplitude components are summed by an adder 57 in the opposite phase, so that an error signal voltage is obtained which indicates an amount of a phase difference. The error signal voltage is passed through a loop filter 58, and is fed back to a VCCG 29 to correct the phase of the replica code sequence. The phase advance (or retardation) time .delta. ranges from 0 to Tc, where Tc is the chip interval.
Applying the CDMA system to cellular communications requires high accuracy transmission power control that keeps constant base station's received levels of signals sent from all the mobile stations. The CDMA system can increase the capacity in terms of the number of subscribers per frequency band as compared with the FDMA system or the TDMA system. This is because conventional systems which employ frequency orthogonality cannot utilize the same carrier frequencies in the contiguous cells, and even space diversity systems cannot reuse the same frequencies within four cells.
In contrast with this, the CDMA system makes it possible to reuse the same carrier frequency in the contiguous cells because the signals of the other communicators are regarded as white noise. Accordingly, the CDMA system can increase the capacity in terms of the number of subscribers as compared with the FDMA system or the TDMA system. If the processing gain is pg, the number of spreading code sequences that completely orthogonalize with each other is pg. This number of the code sequences, however, will be insufficient when information data is spread by using only code sequences of one symbol interval long. To overcome this problem, the number of the spreading codes is increased almost infinitely by superimposing long code sequences of a very long interval over short code sequences of one symbol interval.
Unlike M sequences that have definite autocorrelation characteristics, the autocorrelation of Gold sequences and that of the sequences obtained by superimposing very long code sequences over the Gold sequences will have undesired peaks of considerable amplitudes in addition to the normal correlation peak in one symbol interval. As a result, when the received signal level is low, a lock may be lost in the conventional delay-locked loop using one chip interval lock. Let us formulate the operation principle of the delay-locked loop of FIG. 3. First, the input signal is expressed by the following equation. ##EQU1## where S is average signal power, c(t-.tau..sub.t) is a received spreading code including a propagation delay, m(t-.tau..sub.t) represents data modulation including the propagation delay, .omega..sub.0 is the angular frequency of a carrier, and .OMEGA.(t)=.OMEGA..sub.0 +.THETA..sub.0t is an unknown carrier phase which is represented as the sum of a constant term and a term proportional to the Doppler frequency. The power spectrum density of n(t) is N.sub.0/2. .delta..omega..sub.0 is an angular frequency error between the center frequency of a modulation signal and a local oscillation frequency. In addition, the bandpassed expression of input thermal noise ni(t) is given by ##EQU2## where N.sub.c (t) and N.sub.s (t) are assumed to be approximately and statistically independent and steady. The spreading replica sequence of the advanced phase and that of the retarded phase can be expressed as follows: EQU C(t-.tau..sub.t +.delta.),C(t-.tau..sub.t -.delta.) (2A)
where .tau..sub.t is a propagation delay estimated by the DLL at the receiving side. The crosscorrelation output of the phase detector is expressed as ##EQU3## where K.sub.m is the gain of the phase detector which is assumed to be equal in both branches, and X represents the average of a set.
FIGS. 4A-4B illustrate the autocorrelation outputs in terms of the received chip phase error. Here, EQU .epsilon..sub.t .ident.(.tau..sub.t -.tau..sub.t)/Tc (3A)
is a normalized propagation delay error. H(s) is a lowpass expression of a transfer function H(s) of the bandpass filter, and EQU .epsilon..sub.t.+-. (t-.tau..sub.t .epsilon..sub.t).ident.c(t-.tau..sub.t)c(t-.tau..+-..delta.)-c(t-.tau..sub .t)c(t-.tau..sub.t .+-..delta.) (4)
is a process of a PN sequence.
The output of the square-law detector can be expressed as follows using R.sub.pN.+-. (x) which is a function obtained by shifting the autocorrelation function of PN by a time period of +x. ##EQU4## where EQU m(t)=H.sub..iota. (P)m(t) EQU .epsilon..sub.c.+-. (t,.epsilon..sub.t)=H.sub..iota. (P)[m(t).epsilon..sub.c.+-. (t,.epsilon..sub.t)] EQU N.sub.c.+-. (t)=H.sub..iota. (P)[m(t)c(t-.tau..sub.t .+-..epsilon..sub.t)N.sub.c (t)] EQU N.sub.s.+-. (t)=H.sub..iota. (P)[m(t)c(t-.tau..sub.t .+-..epsilon..sub.t)N.sub.s (t)] (6)
Here, H/(p).times.(t) expresses an output response of the BPF to x(t). If the bandwidth B.sub.L is sufficiently smaller than the chip rate, the effect of the auto-noise caused by the PN sequence on the loop is negligible in the first-order approximation. Neglecting the auto-noise and the secondary harmonic caused by the square-law detection, the input to the loop filter can be expressed by the following equation. EQU e(t).ident.y.sub.-.sup.2 (t)-y.sub.+.sup.2 (t)=SK.sub.m.sup.2 m.sup.2 (t-.tau..sub.t)D(.epsilon..sub.t)+K.sub.m.sup.2 n.sub.e (t,.epsilon..sub.t)(7)
where EQU D(.epsilon..sub.t).ident.R.sup.2 PN-(.epsilon..sub.t)-R.sup.2 PN+.sup.2 (.epsilon..sub.t) (7A)
According to the foregoing, a normalized delay estimate of the output of the spreading code replica generator is expressed by the following equation using e(t). ##EQU5## where F(s) is the transfer function of the loop filter, and K.sub.VCC is the gain of a voltage controller in the VCCG which drives the PN sequence generator. Placing K=Km.sup.2 K.sub.VCC, K represents the loop gain. Substituting equation (7) into (8), ##EQU6## Thus, estimated error .epsilon..sub.t is expressed as ##EQU7## Resolving the first term in the blanket of the above equation into an average value term and modulated auto-noise term gives ##EQU8## where &lt; &gt; expresses an average in time, and ##EQU9## where Sm(f) is a power spectrum density of the data modulation. The M.sub.2 term is the integral of the data modulation power spectrum density over the passband of the filter, and indicates the data modulation power in the passband. Since the bandwidth of the loop is much smaller than the data symbol rate, the auto-noise associated with the second term of equation (11) is negligible.
From equation (10), the following equation is obtained. ##EQU10## where a dot placed over characters represents a time differential, and .eta. is given by ##EQU11##
Briefly, the average of squared tracking jitter due to noise component is expressed as follows: ##EQU12## where B.sub.L is an equivalent noise bandwidth of the LPF, and N.sub.e (.epsilon..sub.t) is expressed as ##EQU13## where f(.epsilon..sub.t) represents a square-law detection curve.
Since the conventional DLL uses the square-law detector as shown in equation (15), the noise component is also squared. This will increase the tracking jitter as shown in equation (14).